Nanoelectronics research centre imec will present at this week's VLSI circuits symposium 2014 (Honolulu, June 13) a low power pipelined SAR (successive-approximation register) ADC (analog to digital converter) in 28nm digital CMOS with record resolution, speed and power performance. The novel ADC targets wireless receivers for next-generation software defined radio, including wireless standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac).
In a software defined radio, the ADC needs high speed, high resolution and high power efficiency in a dynamic solution, supporting high, as well as low bandwidth standards. The pipelined SAR ADC developed by imec and
In a software defined radio, the ADC needs high speed, high resolution and high power efficiency in a dynamic solution, supporting high, as well as low bandwidth standards. The pipelined SAR ADC developed by imec and
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