Digital and Mixed-Signal ASICs
There are purely digital and mixed-signal ASICs. As concerns the redesign of digital ASICs, various methods are available, such as, for instance, mask-programmable and standard-cell technology or replacement with a programmable logic module. A mixed-signal ASIC contains digital modules as well as an analog part of variable size. The redesign effort is reduced by using analog or digital IPs, a database that is as complete as possible, comprehensive and detailed documentation of the ASIC, as well as a testing environment. When implementing a concrete redesign order for a mixed-signal ASIC, MAZeT eliminated the weaknesses of the original ASIC: For example, the previous 0.6 µm CMOS technology was replaced by 0.35 µm CMOS technology, which will be available over the long term. The entire pin assignment was retained despite the improved redesign, allowing the existing printed circuit boards (PCB) to be still used.
Prerequisites for ASIC Redesign
Successful ASIC redesign is subject to several conditions. The more of these are met, the lower the design risk, development time, and redesign costs. The top priority is to provide a technical description including a requirements specification, circuit plan, high-level language description, netlist, and data sheet in order to ensure functional compatibility. The testing vectors and environment are essential for delivering the proof of functionality needed for series production. What is also important is the description of the dynamic behavior as the logic elements such as gates, flip-flops, memory etc. of a new semiconductor technology often exhibit different delay times and the analog transistors display a different electrical behavior, i.e., they represent different models. Other prerequisites include the testing program for the circuit tester, precise documentation of the ASIC's electrical functions, the electrical characterization of the input/output behavior, the supply voltage concept, the ESD and EMC concept, as well as the GDS2 data set.