With the latest version of its Universal Debug Engine® (UDE) PLS Programmierbare Logik & Systeme is providing system developers with comprehensive analysis, test and debugging functions for the latest generation of AURIX™ microcontrollers from Infineon.
The highly integrated multi-core SoCs of the TC4x family, manufactured in 28-nm technology, address a wide range of automotive applications such as e-mobility, ADAS and AI applications and also master highly complex challenges in the area of domain and zone control. At the same time, the devices meet the highest safety requirements with regard to autonomous driving. They consist of up to six powerful main cores based on the Next-Generation TriCore™ v1.8 architecture, a special Cyber-Security Real-Time Module (CSRM), and other new enhancements for high-performance applications. New introductions include the (enhanced) Generic Timer Module (GTM/eGTM) plus AURIX accelerator suite elements, such as converter DSPs (cDSP) at the analog-to-digital converters (ADC), and a Parallel Processing Unit (PPU). This powerful accelerator is based on Synopsys ARC® EV architecture, which enables mathematical modeling of complex heterogeneous systems.
Via its intuitive and thus particularly user-friendly user interface, the UDE enables developers to easily access all TriCore™ v1.8 and special cores of the respective TC4x SoC. The tool allows control of all cores for debugging, testing and in-depth system analyses within a single debugger instance. Therefore, there is no need to open separate debugger instances for the different core architectures such as the Synopsys ARC for the PPU or the GTM. Currently, the UDE allows debugging of C/C++ as well as assembly code, with support for all major compilers, especially those from HighTec, Synopsys and Tasking. Support for the Synopsys MetaWare OpenCL C compiler for PPU code is in preparation. For debugging the SCRM within the UDE, PLS also offers a corresponding extension package.
Depending on the partitioning of the applications running on the TC4x, the cores can be controlled either all together, in groups or even individually by traditional run-mode debugging, i.e. by breakpoints or by single-step operation. By utilizing the chip's own debug logic, UDE allows almost synchronous starting and stopping of the particular cores. Multi-core breakpoints also simplify the debugging of complex applications, especially in shared code. A multi-core breakpoint is always effective, no matter which core is currently executing the specific code.
To ensure the highest level of efficiency, the UDE user interface can be adapted very flexibly to the preferences of the respective user and the specific demands of the current debug or test task. All debugger windows, which display for example source code, internal states such as variables, registers or even graphical visualizations, can be arranged, grouped or even distributed across multiple monitors within the UDE interface in a completely flexible manner. Additionally, with perspectives it is possible to define multiple views within a debugger session and switching between them. This option turns out to be extremely helpful when focusing on a specific debugging task, for example in multicore debugging, when the developer wants to analyze the behavior of a core in detail, or for performance measurements using profiling. Perspectives can be freely created and debugger windows can be inserted and arranged without restrictions in them.
For a fast time-to-market, the UDE can already be used for pre-silicon development. For this purpose, the UDE supports software testing and debugging on virtual prototypes created with the Synopsys Virtualizer Development Kit for AURIX™ TC4x. This enables full-system simulation of the TC4x devices. For software debugging of the TriCore™ v1.8 cores, the UDE also contains the instruction set simulator TSIM.
Later this year, the UDE will also support on-chip and external trace. Then, the already widely used Universal Emulation Configurator (UEC) for flexible definition of trace tasks will also be available for the TC4x. In addition, PLS will provide an adaptation for the serial high-speed trace interface of the new AURIX™ generation for the UAD2next and UAD3+ devices of the Universal Access Device family.
The highly integrated multi-core SoCs of the TC4x family, manufactured in 28-nm technology, address a wide range of automotive applications such as e-mobility, ADAS and AI applications and also master highly complex challenges in the area of domain and zone control. At the same time, the devices meet the highest safety requirements with regard to autonomous driving. They consist of up to six powerful main cores based on the Next-Generation TriCore™ v1.8 architecture, a special Cyber-Security Real-Time Module (CSRM), and other new enhancements for high-performance applications. New introductions include the (enhanced) Generic Timer Module (GTM/eGTM) plus AURIX accelerator suite elements, such as converter DSPs (cDSP) at the analog-to-digital converters (ADC), and a Parallel Processing Unit (PPU). This powerful accelerator is based on Synopsys ARC® EV architecture, which enables mathematical modeling of complex heterogeneous systems.
Via its intuitive and thus particularly user-friendly user interface, the UDE enables developers to easily access all TriCore™ v1.8 and special cores of the respective TC4x SoC. The tool allows control of all cores for debugging, testing and in-depth system analyses within a single debugger instance. Therefore, there is no need to open separate debugger instances for the different core architectures such as the Synopsys ARC for the PPU or the GTM. Currently, the UDE allows debugging of C/C++ as well as assembly code, with support for all major compilers, especially those from HighTec, Synopsys and Tasking. Support for the Synopsys MetaWare OpenCL C compiler for PPU code is in preparation. For debugging the SCRM within the UDE, PLS also offers a corresponding extension package.
Depending on the partitioning of the applications running on the TC4x, the cores can be controlled either all together, in groups or even individually by traditional run-mode debugging, i.e. by breakpoints or by single-step operation. By utilizing the chip's own debug logic, UDE allows almost synchronous starting and stopping of the particular cores. Multi-core breakpoints also simplify the debugging of complex applications, especially in shared code. A multi-core breakpoint is always effective, no matter which core is currently executing the specific code.
To ensure the highest level of efficiency, the UDE user interface can be adapted very flexibly to the preferences of the respective user and the specific demands of the current debug or test task. All debugger windows, which display for example source code, internal states such as variables, registers or even graphical visualizations, can be arranged, grouped or even distributed across multiple monitors within the UDE interface in a completely flexible manner. Additionally, with perspectives it is possible to define multiple views within a debugger session and switching between them. This option turns out to be extremely helpful when focusing on a specific debugging task, for example in multicore debugging, when the developer wants to analyze the behavior of a core in detail, or for performance measurements using profiling. Perspectives can be freely created and debugger windows can be inserted and arranged without restrictions in them.
For a fast time-to-market, the UDE can already be used for pre-silicon development. For this purpose, the UDE supports software testing and debugging on virtual prototypes created with the Synopsys Virtualizer Development Kit for AURIX™ TC4x. This enables full-system simulation of the TC4x devices. For software debugging of the TriCore™ v1.8 cores, the UDE also contains the instruction set simulator TSIM.
Later this year, the UDE will also support on-chip and external trace. Then, the already widely used Universal Emulation Configurator (UEC) for flexible definition of trace tasks will also be available for the TC4x. In addition, PLS will provide an adaptation for the serial high-speed trace interface of the new AURIX™ generation for the UAD2next and UAD3+ devices of the Universal Access Device family.
