Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Toshiba Information Systems (Japan) has standardized on the Verification Methodology Manual for Low Power (VMM-LP) to verify its low power chip designs. Incorporating industry best practices from the collective reallife experiences of more than 30 companies, the VMM-LP provides a framework for accelerating the verification of low power designs. Toshiba Information Systems (Japan) used Synopsys' voltageaware VCS® functional verification solution with MVSIM and VMM-LP to deploy a uniform, structured and repeatable verification methodology across its low power design projects.
Toshiba Information Systems (Japan) performs design and verification services for low power designs with complex low power architectures employing multiple voltage domains and advanced design techniques. The functional modes of the design map to several power modes, and a single undetected bug may cause the entire system to not meet power requirements or to even malfunction. Verification of all the design's power modes requires a rigorous and methodical approach to ensure bugfree silicon. One of the most timeconsuming aspects of lowpower verification is the development and deployment of a reusable testbench across multiple projects. Leveraging the documented methodology in the VMM-LP book and using the low power base classes, Toshiba Information Systems (Japan) was successful in verifying the low power functionality of a mobile multimedia application and setting up a testbench infrastructure that can be quickly adapted to other low power projects.
"We are seeing a rapid increase in the complexity of low power designs in Japan," said Tomoji Takada, general manager, LSI Solutions Division, Toshiba Information Systems (Japan). "In addition to using a voltageaware verification solution provided by VCS with MVSIM, we needed a structured methodology to enable efficient lowpower verification and ensure highquality designs. VMM-LP provided us this structured methodology. It also helped us to find ways to leverage our verification setup and build upon our verification expertise in OCP and AMBAbased environments and extend it from one low power project to the next."
"VMM-LP addresses the market need for innovation in low power verification," said Manoj Gandhi, senior vice president and general manager, Verification Group, Synopsys, Inc. "Our collaboration with Toshiba Information Systems (Japan) will help to deploy the VMM-LP methodology on many design projects. Synopsys will continue to invest and collaborate with industry leaders in developing and enabling nextgeneration verification methodologies."
About the VMM for Low Power
The lead authors of the VMM-LP book are Srikanth Jadcherla, group director of Research and Development at Synopsys and founder of ArchPro Design Automation, Inc., which Synopsys acquired in 2007; Janick Bergeron, Synopsys Fellow and moderator of the Verification Guild web site; Yoshio Inoue, chief engineer, Design Technology Division, Renesas Technology Corp., and David Flynn, ARM fellow and coauthor of the Low Power Methodology Manual (LPMM) [Springer].
The VMM-LP book defines a robust and scalable verification architecture that can be used to quickly setup and complete verification of low power designs. The methodology addresses all aspects of functional verification of power management functions, including suggestions for static versus dynamic verification, designforverification techniques, and use of assertions and coverage metrics to achieve rapid verification closure. VMM-LP also defines SystemVerilog base classes that are power aware and enable setup of a reusable testbench.
Availability
The VMM-LP book is available today for purchase through the VMM Central Web site (http://www.vmmcentral.org/...). Additionally, customers can download a PDF version of the book and register to receive notification about the availability of the source code for the VMM-LP SystemVerilog base classes from VMM Central.
Toshiba Information Systems (Japan) performs design and verification services for low power designs with complex low power architectures employing multiple voltage domains and advanced design techniques. The functional modes of the design map to several power modes, and a single undetected bug may cause the entire system to not meet power requirements or to even malfunction. Verification of all the design's power modes requires a rigorous and methodical approach to ensure bugfree silicon. One of the most timeconsuming aspects of lowpower verification is the development and deployment of a reusable testbench across multiple projects. Leveraging the documented methodology in the VMM-LP book and using the low power base classes, Toshiba Information Systems (Japan) was successful in verifying the low power functionality of a mobile multimedia application and setting up a testbench infrastructure that can be quickly adapted to other low power projects.
"We are seeing a rapid increase in the complexity of low power designs in Japan," said Tomoji Takada, general manager, LSI Solutions Division, Toshiba Information Systems (Japan). "In addition to using a voltageaware verification solution provided by VCS with MVSIM, we needed a structured methodology to enable efficient lowpower verification and ensure highquality designs. VMM-LP provided us this structured methodology. It also helped us to find ways to leverage our verification setup and build upon our verification expertise in OCP and AMBAbased environments and extend it from one low power project to the next."
"VMM-LP addresses the market need for innovation in low power verification," said Manoj Gandhi, senior vice president and general manager, Verification Group, Synopsys, Inc. "Our collaboration with Toshiba Information Systems (Japan) will help to deploy the VMM-LP methodology on many design projects. Synopsys will continue to invest and collaborate with industry leaders in developing and enabling nextgeneration verification methodologies."
About the VMM for Low Power
The lead authors of the VMM-LP book are Srikanth Jadcherla, group director of Research and Development at Synopsys and founder of ArchPro Design Automation, Inc., which Synopsys acquired in 2007; Janick Bergeron, Synopsys Fellow and moderator of the Verification Guild web site; Yoshio Inoue, chief engineer, Design Technology Division, Renesas Technology Corp., and David Flynn, ARM fellow and coauthor of the Low Power Methodology Manual (LPMM) [Springer].
The VMM-LP book defines a robust and scalable verification architecture that can be used to quickly setup and complete verification of low power designs. The methodology addresses all aspects of functional verification of power management functions, including suggestions for static versus dynamic verification, designforverification techniques, and use of assertions and coverage metrics to achieve rapid verification closure. VMM-LP also defines SystemVerilog base classes that are power aware and enable setup of a reusable testbench.
Availability
The VMM-LP book is available today for purchase through the VMM Central Web site (http://www.vmmcentral.org/...). Additionally, customers can download a PDF version of the book and register to receive notification about the availability of the source code for the VMM-LP SystemVerilog base classes from VMM Central.
